|========================+==========================|=========================|
|Function                | NMOS 6502                | W65C02S                 |
|========================+==========================+=========================|
|Indexed addressing      | Extra read of invalid    | Extra read of last      |
|across page boundary    | address.                 | instruction byte        |
|------------------------+--------------------------+-------------------------|
|execution of invalid    | Some terminate only by   | All are NOPs (reserved  |
|opcodes                 | reset; results are       | for future use).        |
|                        | undefined.               |                         |
|------------------------+--------------------------+-------------------------|
|Jump indirect,          | Page address does not    | Page address increments |
|operand=XXFF            | increment.               | one additional cycle.   |
|------------------------+--------------------------+-------------------------|
|Read/Modify/Write       | One read and two write   | Two read and one write  |
|instruction at          | cycles.                  | cycle.                  |
|effective address       |                          |                         |
|------------------------+--------------------------+-------------------------|
|Decimal flag            | Indeterminate after      | Initialized to binary   |
|                        | reset.                   | mode (D=0) after reset  |
|                        |                          | and interrupts.         |
|------------------------+--------------------------+-------------------------|
|Flags after decimal     | Invalid N, V and Z flags | Valid flags.  One       |
|operation               |                          | additional cycle.       |
|------------------------+--------------------------+-------------------------|
|Interrupt after fetch   | Interrupt vector is      | BRK is executed, then   |
|of BRK instruction      | loaded; BRK vector is    | interrupt is executed.  |
|                        | ignored.                 |                         |
|------------------------+--------------------------+-------------------------|
|Ready                   | Input.                   | Bidirectional, WAI      |
|                        |                          | instruction pulls low.  |
|------------------------+--------------------------+-------------------------|
|Read/Modify/Write       | Seven cycles             | Six cycles.             |
|instructions absolute   |                          |                         |
|indexed in same page    |                          |                         |
|------------------------+--------------------------+-------------------------|
|Oscillator              | Requires external active | Crystal or RC network   |
|                        | components.              | will oscillate when     |
|                        |                          | connected between       |
|                        |                          | PHI2(IN) and PHI2(OUT). |
|------------------------+--------------------------+-------------------------|
|Assertions of Ready     | Ignored.                 | Stops processor during  |
|(RDY) during write      |                          | PHI2; WAI instruction   |
|operations              |                          | pulls RDY low.          |
|------------------------+--------------------------+-------------------------|
|Clock inputs            | Two non-overlapping      | PHI2(IN) is the only    |
|                        | clock inputs (PHI1 and   | required clock.         |
|                        | PHI2) are required.      |                         |
|------------------------+--------------------------+-------------------------|
|Unused input-only pins  | Must be connected to low | Connected internally by |
|                        | impedance signal to      | high-resistance to VDD  |
|                        | avoid noise problems.    | (approx. 20 Megohm)     |
|------------------------+--------------------------+-------------------------|